Advanced Digital Design with the Verilog HDL 2/e (絕)
- 20本以上，享 8.5折
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- 一般書籍
- ISBN：9780132465571
- 作者：Michael D. Ciletti
- 版次：2
- 年份：2011
- 出版商：Pearson Education
- 頁數/規格：983頁/平裝單色
書籍介紹
本書特色
目錄
Description
This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.
This book builds on the student's background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but selective manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.
Features
New to This Edition
- Provides a brief review of basic principles in combinational and sequential logic
- Focuses on modern digital design methodology
- Demonstrates the utility of ASM and ASMD charts for behavioral modeling
- Clearly distinguishes between synthesizable and nonsynthesizable loops
- Provides practical treatment of timing analysis, fault simulation, testing, and design for testability, with examples
- Provides several problems with a wide range of difficulty after each chapter
- Combines a solution manual with an on-line repository of additional worked exercises
- Lists an index of all models developed in the examples
- Includes a set of FPGA-based, lab-ready exercises linked to the book (e.g. arithmetic and logic unit (ALU), programmable lock, a keypad scanner with a FIFO, a serial communications link with error correction, an SRAM controller, and first in, first out (FIFO) memory, RISC CPU, and FIFO)
New to This Edition
- Exploits key features of Verilog 2001, 2005
- Illustrates and promotes a synthesis-ready style of register transfer level (RTL) and algorithmic modeling with Verilog 2001, 2005
- Provides an in-depth treatment of algorithms and architectures for digital machines (e.g. an image processor, digital filters, and circular buffers) with Verilog 2001, 2005
- Includes comprehensive design examples (e.g. a RISC machine and various datapath controllers) with Verilog 2001, 2005
- Includes numerous annotated and explained graphical illustrations of simulation results
- Contains over 150 fully verified examples with Verilog 2001, 2005
- Contains a worked example with JTAG and BIST for testing with Verilog 2001, 2005
- Contains an Appendix with full formal syntax of the Verilog 2001, 2005 HDL
- Treats asynchronous and synchronous FIFOs
Table of Contents
1 Introduction to Digital Design Methodology
2 Review of Combinational Logic Design
3 Fundamentals of Sequential Logic Design
4 Introduction to Logic Design with Verilog
5 Logic Design with Behavioral Models of Combinational and Sequential Logic
6 Synthesis of Combinational and Sequential Logic
7 Design and Synthesis of Datapath Controllers
8 Programmable Logic and Storage Devices
9 Algorithms and Architectures for Digital Processors
10 Architectures for Arithmetic Processors
11 Postsynthesis Design Tasks
1 Introduction to Digital Design Methodology
2 Review of Combinational Logic Design
3 Fundamentals of Sequential Logic Design
4 Introduction to Logic Design with Verilog
5 Logic Design with Behavioral Models of Combinational and Sequential Logic
6 Synthesis of Combinational and Sequential Logic
7 Design and Synthesis of Datapath Controllers
8 Programmable Logic and Storage Devices
9 Algorithms and Architectures for Digital Processors
10 Architectures for Arithmetic Processors
11 Postsynthesis Design Tasks
