Pentium Pro and Pentium II System Architecture 2/e(絕)
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- 一般書籍
- ISBN：9780201309737
- 作者：MindShare Inc.
- 版次：2
- 年份：1998
- 出版商：Pearson Education
- 頁數/規格：588頁
書籍介紹
目錄
作者介紹
Description
Written for computer hardware and software engineers, this book offers insight into how the Pentium Pro and Pentium II family of processors translates legacy x86 code into RISC instructions, executes them out-of-order, and then reassembles the result to match the original program flow. In detailing the Pentium Pro and Pentium II processors' internal operations, the book reveals why the processors generate various transaction types and how they monitor bus traffic generated by other entities to ensure cache consistency.
This new edition includes comprehensive coverage of the Pentium II processor. It highlights the differences between the Pentium Pro and Pentium II processors, in particular, the Slot 1 connector and the processor cartridge design utilized by the Pentium II and intended for use in future Intel processors. It features the Pentium II's support for the MMX instruction set and registers, and shows how it is optimized for 16-bit code execution. This book also describes the Pentium II's L2 cache and its support for power-conservation modes.
Pentiumi Pro and Pentiumi II System Architecture, Second Edition, also covers:
The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware and explains thoroughly the architecture, features, and operations of systems built using one particular type of chip or hardware specification.
Written for computer hardware and software engineers, this book offers insight into how the Pentium Pro and Pentium II family of processors translates legacy x86 code into RISC instructions, executes them out-of-order, and then reassembles the result to match the original program flow. In detailing the Pentium Pro and Pentium II processors' internal operations, the book reveals why the processors generate various transaction types and how they monitor bus traffic generated by other entities to ensure cache consistency.
This new edition includes comprehensive coverage of the Pentium II processor. It highlights the differences between the Pentium Pro and Pentium II processors, in particular, the Slot 1 connector and the processor cartridge design utilized by the Pentium II and intended for use in future Intel processors. It features the Pentium II's support for the MMX instruction set and registers, and shows how it is optimized for 16-bit code execution. This book also describes the Pentium II's L2 cache and its support for power-conservation modes.
Pentiumi Pro and Pentiumi II System Architecture, Second Edition, also covers:
- the relationship of Pentium Pro and Pentium II processors to other processors, PCI bridges, caches, and memory
- detailed descriptions of the data, code, and L2 caches
- power-on configuration and processor startup
- transaction deferral
- instruction, register set, paging, and interrupt enhancements to the Pentium Pro and Pentium II
- BIOS Update Feature
- Machine Check Architecture
- performance monitoring and the Time Stamp Counter
- MMX register and instruction set supported by the Pentium II
- overview of the Intel 450KX, 450GX, and 440FX chipsets
The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware and explains thoroughly the architecture, features, and operations of systems built using one particular type of chip or hardware specification.
Table of Contents
I. SYSTEM OVERVIEW.
1. System Overview.
II. PROCESSOR'S HARDWARE CHARACTERISTICS.
2. Processor Overview.
3. Processor Power-On Configuration.
4. Processor Startup.
5. The Fetch, Decode, Execute Engine.
6. Rules of Conduct.
7. The Processor Caches.
8. Bus Electrical Characteristics.
9. Bus Basics.
10. Obtaining Bus Ownership.
11. The Request and Error Phases.
12. The Snoop Phase.
13. The Response and Data Phases.
14. Transaction Deferral.
15. IO Transactions.
16. Central Agent Transactions.
17. Other Signals.
III. PENTIUM II PROCESSOR.
18. Pentium II Processor.
IV. PROCESSOR'S SOFTWARE CHARACTERISTICS.
19. Instruction Set Enhancements.
20. Register Set Enhancements.
21. BIOS Update Feature.
22. Paging Enhancements.
23. Interrupt Enhancements.
24. Machine Check Architecture.
25. Performance Monitoring and Timestamp.
26. MMX: Matrix Math Extensions.
I. SYSTEM OVERVIEW.
1. System Overview.
II. PROCESSOR'S HARDWARE CHARACTERISTICS.
2. Processor Overview.
3. Processor Power-On Configuration.
4. Processor Startup.
5. The Fetch, Decode, Execute Engine.
6. Rules of Conduct.
7. The Processor Caches.
8. Bus Electrical Characteristics.
9. Bus Basics.
10. Obtaining Bus Ownership.
11. The Request and Error Phases.
12. The Snoop Phase.
13. The Response and Data Phases.
14. Transaction Deferral.
15. IO Transactions.
16. Central Agent Transactions.
17. Other Signals.
III. PENTIUM II PROCESSOR.
18. Pentium II Processor.
IV. PROCESSOR'S SOFTWARE CHARACTERISTICS.
19. Instruction Set Enhancements.
20. Register Set Enhancements.
21. BIOS Update Feature.
22. Paging Enhancements.
23. Interrupt Enhancements.
24. Machine Check Architecture.
25. Performance Monitoring and Timestamp.
26. MMX: Matrix Math Extensions.
MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.
